Improvement of SRAM-based failure analysis calibrated IDDQ testing

Publication Year:
1996
Usage 129
Abstract Views 129
Repository URL:
http://hdl.handle.net/1969.1/ETD-TAMU-1996-THESIS-B353
Author(s):
Balachandran, Hariharan
Publisher(s):
Texas A&M University
Tags:
electrical engineering.; Major electrical engineering.
thesis / dissertation description
For any semiconductor industry to be competitive, they should be able to meet with the continuous increasing demand in integrated circuits(IC) functionality. Their time-to-market period should also be optimally small. This necessitates the usage of sophisticated processing tools that increases the manufacturing cost. Increasing the manufacturing yield will reduce the effective manufacturing cost per die. Hence integrated circuit manufacturers try to improve yield to profitable levels in a short time frame and to maintain or improve the yields once they are achieved. Yields can be substantially increased when one is able to identify the causes for yield loss, In this research a methodology to identify integrated circuit yield detractors using SRAM functional test results in combination with a defect-bitmap dictionary. We investigate the accuracy of the defect classification under different forms of voltage testing and current testing. In particular we investigate the benefit of using multiple Iddq current levels calibrated to remove normal parametric variations. We also investigate the effects of unmodeled defects and the ability to identify cases of certain and uncertain diagnosis. We have experimentally validated our approach using a production microprocessor cache.