A 45.8 fJ/Step, energy-efficient, differential SAR capacitance-to-digital converter for capacitive pressure sensing

Citation data:

Sensors and Actuators A: Physical, ISSN: 0924-4247, Vol: 245, Page: 10-18

Publication Year:
2016
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Citations 8
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Repository URL:
http://hdl.handle.net/10754/621485
DOI:
10.1016/j.sna.2016.04.038
Author(s):
Alhoshany, Abdulaziz; Omran, Hesham; Salama, Khaled N.
Publisher(s):
Elsevier BV
Tags:
Materials Science; Physics and Astronomy; Engineering; Capacitance-to-digital converter (CDC); Capacitive sensor interface; CMOS; Current-starved inverter; Energy-efficient
article description
An energy-efficient readout circuit for a capacitive sensor is presented. The capacitive sensor is digitized by a 12-bit energy efficient capacitance-to-digital converter (CDC) that is based on a differential successive-approximation architecture. This CDC meets extremely low power requirements by using an operational transconductance amplifier (OTA) that is based on a current-starved inverter. It uses a charge-redistribution DAC that involves coarse-fine architecture. We split the DAC into a coarse-DAC and a fine-DAC to allow a wide capacitance range in a compact area. It covers a wide range of capacitance of 16.14 pF with a 4.5 fF absolute resolution. An analog comparator is implemented by cross-coupling two 3-input NAND gates to enable power and area efficient operation. The prototype CDC was fabricated using a standard 180 nm CMOS technology. The 12-bit CDC has a measurement time of 42.5 μs, and consumes 3.54 μW and 0.29 μW from analog and digital supplies, respectively. This corresponds to a state-of-the-art figure-of-merit (FoM) of 45.8 fJ/conversion-step.