Sub-15 nm nano-pattern generation by spacer width control for high density precisely positioned self-assembled device nanomanufacturing

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Proceedings of the IEEE Conference on Nanotechnology, ISSN: 1944-9399, Page: 1-5

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Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa
Institute of Electrical and Electronics Engineers (IEEE)
Chemical Engineering; Engineering; Materials Science; Physics and Astronomy
conference paper description
We present a conventional micro-fabrication based thin film vertical sidewall (spacer) width controlled nano-gap fabrication process to create arrays of nanopatterns for high density precisely positioned self-assembled nanoelectronics device integration. We have used conventional optical lithography to create base structures and then silicon nitride (Si N) based spacer formation via reactive ion etching. Control of SiN thickness provides accurate control of vertical sidewall (spacer) besides the base structures. Nano-gaps are fabricated between two adjacent spacers whereas the width of the gap depends on the gap between two adjacent base structures minus width of adjacent spacers. We demonstrate the process using a 32 nm node complementary metal oxide semiconductor (CMOS) platform to show its compatibility for very large scale heterogeneous integration of top-down and bottom-up fabrication as well as conventional and selfassembled nanodevices. This process opens up clear opportunity to overcome the decade long challenge of high density integration of self-assembled devices with precise position control. © 2012 IEEE.