Machine Learning-Based Fault Tolerance Techniques for VLSI Circuit Design
Lecture Notes in Electrical Engineering, ISSN: 1876-1119, Vol: 1274 LNEE, Page: 1359-1369
2025
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Example: if you select the 1-year option for an article published in 2019 and a metric category shows 90%, that means that the article or review is performing better than 90% of the other articles/reviews published in that journal in 2019. If you select the 3-year option for the same article published in 2019 and the metric category shows 90%, that means that the article or review is performing better than 90% of the other articles/reviews published in that journal in 2019, 2018 and 2017.
Citation Benchmarking is provided by Scopus and SciVal and is different from the metrics context provided by PlumX Metrics.
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Conference Paper Description
In the dynamic landscape of Very Large-Scale Integration (VLSI) circuit design, the relentless pursuit of enhanced performance and fault tolerance confronts challenges arising from shrinking transistor sizes and heightened component density. This paper explores the integration of machine learning (ML) techniques into VLSI fault tolerance, in a new era of adaptability and resilience. Various ML-driven fault tolerance strategies are investigated, encompassing anomaly detection, supervised learning for fault classification, fault localization and diagnosis, reconfiguration and self-repair mechanisms, predictive maintenance, adaptive testing, and reliability modelling. By leveraging data-driven insights, these techniques promise to revolutionize VLSI circuit design, mitigating the impact of faults and setting the stage for future advancements.
Bibliographic Details
http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=85208197058&origin=inward; http://dx.doi.org/10.1007/978-981-97-8043-3_195; https://link.springer.com/10.1007/978-981-97-8043-3_195; https://dx.doi.org/10.1007/978-981-97-8043-3_195; https://link.springer.com/chapter/10.1007/978-981-97-8043-3_195
Springer Science and Business Media LLC
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