Current steering high-speed DAC: Architecture analysis and simulation results
Proceedings of the IEEE 2nd Dallas CAS Workshop on Low Power/Low Voltage Mixed-Signal Circuits and Systems, DCAS 2001, Page: 27-30
2001
- 1Citations
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Example: if you select the 1-year option for an article published in 2019 and a metric category shows 90%, that means that the article or review is performing better than 90% of the other articles/reviews published in that journal in 2019. If you select the 3-year option for the same article published in 2019 and the metric category shows 90%, that means that the article or review is performing better than 90% of the other articles/reviews published in that journal in 2019, 2018 and 2017.
Citation Benchmarking is provided by Scopus and SciVal and is different from the metrics context provided by PlumX Metrics.
Metrics Details
- Citations1
- Citation Indexes1
Conference Paper Description
A DAC architecture based on the current steering method is presented. The proposed architecture exploits the oversampling and uses a MASH like configuration. The DAC requires to use two current steering 5-bit D/A converters whose current references are properly scaled. The two output currents are summed at the output node to achieve the output signal. With an oversampling factor equal to 8 and 40 MHz band-width (clock frequency 640 MHz) it is possible to reach an SNR as large as 72 dB.
Bibliographic Details
Institute of Electrical and Electronics Engineers (IEEE)
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