A 79.3fs Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique
Digest of Technical Papers - Symposium on VLSI Technology, ISSN: 0743-1562, Page: 1-2
2024
- 1Citations
- 9Captures
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Conference Paper Description
This work presents a fractional- N digital PLL leveraging a digital-to-time converter (DTC) chopping technique to improve spectral purity and jitter. By randomly moving the DTC between the reference and divider paths of the PLL, the fractional spurs induced by DTC non-linearity and the DTC flicker noise are suppressed. The synthesizer, fabricated in 28nm CMOS, achieves 79.3fs jitter and -63.6dBc fractional spur at 9.275GHz near-integer channels.
Bibliographic Details
Institute of Electrical and Electronics Engineers (IEEE)
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