A hybrid test architecture to reduce test application time in full scan sequential circuits

Citation data:

Proceedings of INDICON 2009 - An IEEE India Council Conference, Page: 1-4

Publication Year:
2009
Usage 435
Downloads 371
Abstract Views 64
Citations 4
Citation Indexes 4
Repository URL:
https://digitalcommons.unl.edu/cseconfwork/2
DOI:
10.1109/indcon.2009.5409404
Author(s):
Ghosh, Priyankar; Mitra, Srobona; Sengupta, Indranil; Bhattacharya, Bhargab B.; Seth, Sharad C.
Publisher(s):
Institute of Electrical and Electronics Engineers (IEEE)
Tags:
Computer Science; Engineering; Materials Science; ATPG; DFT; BIST; LFSR; and MISR; Computer Sciences
conference paper description
Full scan based design technique is widely used to alleviate the complexity of test generation for sequential circuits. However, this approach leads to substantial increase in test application time, because of serial loading of vectors. Although BIST based approaches offer faster testing, they usually suffer from low fault coverage. In this paper, we propose a hybrid test architecture, which achieves significant reduction in test application time. The test suite consists of: (i) some external deterministic test vectors to be scanned in, and (ii) internally generated responses of the CUT to be re-applied as tests iteratively, in functional (non-scan) mode. The proposed architecture uses only combinational ATPG to hybridize deterministic testing and test per clock BIST, and thus makes good use of both scan based and non-scan testing. We also present a bipartite graph based heuristic to select the deterministic test vectors and sequential fault simulation technique is used to perform the exact analysis on detected faults during the re-application of internally generated responses of the CUT during testing. Experimental results on ISCAS-89 benchmark circuits show the efficacy of the heuristic and reveal a significant reduction of test application time.