Characterization of an Integrated Circuit with Respect to Electrostatic Discharge-Induced Soft Failures

Publication Year:
2016
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Downloads 90
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Repository URL:
http://scholarsmine.mst.edu/doctoral_dissertations/2543
Author(s):
Orr, Benjamin J.
Publisher(s):
Missouri University of Science and Technology
Tags:
Electrostatic Discharge; SEED; Soft Failure; Electrostatic Discharge; SEED; Soft Failure; Electrical and Computer Engineering
thesis / dissertation description
"This research proposal presents a methodology whereby an integrated circuit (IC) can be characterized with respect to soft-failures induced by Electrostatic Discharge (ESD)-like events. This methodology uses an exclusively "black-box" approach to determine the response of an IC in a system-level environment, thereby allowing it to be implemented without intimate knowledge of the DUT IC. Results from this methodology can be referenced during system design to raise awareness of specific vulnerabilities of the core system ICs.During work on this methodology, several sub topics have been explored and developed in the field of system-level ESD. Sections 2 and 3 introduce two topics which were developed to facilitate the generation and expression of IC pin models. Papers 1 and 2 introduce injection methods for characterizing complete systems on an interface-by-interface basis and form the foundation for the following works. Papers 2 and 3 mirror Papers 1 and 2 but instead shift focus away from the system as a whole and outline methods for characterizing the integrated circuits directly. Finally, Section 4 outlines a model method which can be used to describe the failures found in Paper 4 in circuit simulation, rounding out the work. Additional measurements which were unable to be included in Paper 4 are included in Appendices A, B, and C"--Abstract, page iv.