A synthesizable VHDL model of the multicast input-indexed switch

With the advent of increasing multicast applications in Asynchronous Transfer Mode (ATM), transmission of data experiences problems such as high cell loss and low throughput. These problems are evident especially in high proportions of multicast. As a result, high delay in data transfer is experienced. Because of this, ATM data transmission requires a switching algorithm that can efficiently handle data at a faster rate even with increasing multicast proportions. The Multicast Input-Indexed Switch is an ATM switch that has proven to be an efficient way to switch ATM cells. However, the Input-Indexed Switch is currently software-based which requires the use of the microprocessor in its operations. As a result, the microprocessor serves to be the bottleneck of the operations of the whole-system. This, however, causes additional delay. To address this current problem, a hardware implementation of the switch is seen to optimize the performance of the Input-Indexed Switch as there will be an independent processor in switching ATM cells. Thus, this thesis is focused mainly in the synthesizability of a 2 X 2 Multicast Input-Indexed switch through the use of the Xilinx XC4025E Field Programmable Gate Array (FPGA). This is an innovation of the software-based Input-Indexed Switch as this will take into consideration the feasibility of the said switch to be implemented in hardware.