10-bit C2C DAC Design in 65nm CMOS Technology
2019
- 4,468Usage
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Example: if you select the 1-year option for an article published in 2019 and a metric category shows 90%, that means that the article or review is performing better than 90% of the other articles/reviews published in that journal in 2019. If you select the 3-year option for the same article published in 2019 and the metric category shows 90%, that means that the article or review is performing better than 90% of the other articles/reviews published in that journal in 2019, 2018 and 2017.
Citation Benchmarking is provided by Scopus and SciVal and is different from the metrics context provided by PlumX Metrics.
Metrics Details
- Usage4,468
- Downloads4,072
- 4,072
- Abstract Views396
Thesis / Dissertation Description
Many wired and wireless communication systems require high-speed and high-performance data converters. These data converters act as bridge between digital signal processing blocks and power amplifiers. However, these data converters have been the bottleneck in the communication systems. This thesis presents the design of a 10-bit C2C digital to analog converter (DAC) for high resolution, wide bandwidth and low power consumption applications. The DAC is implemented in CMOS 65nm technology. The SFDR of this C2C DAC is 71.95dB at 500MHz input frequency and consumes 88.14µW of power with ENOB as 11.65 with 1.0GHz sample frequency with 0.31LSB of INL and 0.5LSB of DNL. A 10-bit SAR ADC is designed using this proposed C2C DAC with 427.4µW of power consumption at 1.0V voltage supply.
Bibliographic Details
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