Device physics studies of III-V and silicon MOSFETs for digital logic

III-V's are currently gaining a lot of attraction as possible MOSFET channel materials due to their high intrinsic mobility. Several challenges, however, need to be overcome before III-V's can replace silicon (Si) in extremely scaled devices. The effect of low density-of-states of III-V materials is investigated by analyzing the semiconductor capacitance for different device structures and scaling. Solid solubility limit of dopants in the III-V materials are also significantly lower than that in Si, causing high series resistance, and transconductance degradation due to source exhaustion. The metallic source/drain Schottky barrier MOSFET is explored as an alternative to effectively eliminate these issues. The performance of a Si channel SOI MOSFET fabricated at IBM is analyzed and interpreted using ballistic transport. The ballistic ratio and extracted mean free paths demonstrate that scattering effects cannot be ignored in modern Si channel devices. Scattering has been implemented within the non-equilibrium Green's function (NEGF) framework to investigate effects of phonon and surface roughness scattering on device performance. The computational complexity is greatly reduced by analytically integrating over the transverse (width) dimension, making it possible to include scattering in planar FETs. The model has been carefully benchmarked with analytical formulas and Boltzmann transport calculations (2-D Monte Carlo results) for simple potential profiles. The scattering model is used to study the role of phonon scattering on the on-state characteristics of Si channel devices. Finally, the role of surface roughness scattering and its implementation issues within NEGF is discussed.