Algorithmic and architectural techniques for low-power digital signal processing

We present new approaches which can be used to reduce power consumption and/or increase speed of DSP algorithms. Two main ideas are presented; low power quantization, and, computational redundancy removal. The first approach reduces dynamic power consumption of DSP algorithms by trading-off accuracy. A general mathematical frame-work is developed which describes the nature of low-power quantizations and relates these to optimal solutions of constrained least-squares (CLS) problems in the context of FIR digital filter implementation. Arithmetic architectures which validate our dynamic power reduction approaches are also presented. In particular, we present low-switching array multipliers which are hybrids of LSB-first and MSB-first array-multipliers. A detailed switching activity analysis of variants of array multiplier and a 4:2 compressor based tree multiplier shows that various architectures are suitable for various applications based on the statistical properties of signals processed. In the second part, we address reducing computational redundancy by efficiently sharing computation. This approach reduces the complexity of DSP algorithms without compromising performance. We show that common DSP tasks can be expressed as multiplication of vectors by scalars and by using a graph theoretic approach, one can obtain a solution which efficiently shares computation to eliminate all multipliers from the algorithm. We demonstrate this point by obtaining very low-complexity multiplierless filters. New multiplication strategies are proposed which reduce redundant computation from such operations, thereby resulting in a low-power and/or high speed implementation. The idea of increased computation sharing by introducing further quantizations is also presented and explored for low-complexity design.