A system-on-chip (SoC) digital interface IP core.

The work presented in this thesis describes a digital interface Intellectual Property (IP) core, for use in a System-on-Chip (SoC) environment. This IP core allows the main SoC bus to read and write to peripheral devices, such as A/D and D/A converters, respectively. The microprocessor IP core typically defines the properties required for the main SoC bus. In the thesis the system bus requirements are based on the use of the ARM IP microprocessor core (V2.0). Both high performance bus (AHB) and peripheral bus (APB) specifications are available, together with state transaction specifications for bridging between the two bus systems. Peripheral IP cores connect to the APB bus, which interconnects to the APB port on the interface (bridging) IP core. This thesis develops a high level Verilog description of an interface (bridging) IP core and a Verilog description of related interface circuitry that would be resident in the peripheral IP cores. The interface IP core has both an AHB port and an APB port. The Verilog description of the interface (bridging) IP core and the circuitry resident in the peripheral IP core have both been mapped to a 0.35-micron CMOS technology. The interface core is comprised of 1612 elements consisting of logic gates, multiplexors, inverters, and shift-registers. Source: Masters Abstracts International, Volume: 41-04, page: 1163. Adviser: W. C. Miller. Thesis (M.A.Sc.)--University of Windsor (Canada), 2002.