Hardware implementation of triply selective rayleigh fading channel simulators
ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings, ISSN: 1520-6149, Page: 1498-1501
2010
- 4Citations
- 6Usage
- 3Captures
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Metrics Details
- Citations4
- Citation Indexes4
- CrossRef1
- Usage6
- Downloads6
- Captures3
- Readers3
Conference Paper Description
In this paper, we implement a real-time hardware triply selective Rayleigh fading simulator. This simulator incorporates the inter-tap and spatial correlation matrices into multiple uncorrelated frequency-flat Rayleigh fading waveforms (including temporal correlation) to simulate a multiple-input multiple-output (MIMO) triply selective Rayleigh fading channel. In the correlation incorporation procedure, this simulator uses a Kronecker product method to save a large amount of hardware memories. Occupying 34% hardware resources of one Stratix III FPGA chip, this simulator can simulate 4 x 4 MIMO fading channels with 10 correlated delay-taps per subchannel in real-time for a symbol rate of 3.69 μs. Accuracy of this simulator is proved by comparing the statistical properties of its outputs to corresponding theoretical values, and they match perfectly. ©2010 IEEE.
Bibliographic Details
http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=78049392581&origin=inward; http://dx.doi.org/10.1109/icassp.2010.5495499; http://ieeexplore.ieee.org/document/5495499/; http://xplorestaging.ieee.org/ielx5/5487364/5494886/05495499.pdf?arnumber=5495499; https://scholarsmine.mst.edu/ele_comeng_facwork/6127; https://scholarsmine.mst.edu/cgi/viewcontent.cgi?article=7156&context=ele_comeng_facwork
Institute of Electrical and Electronics Engineers (IEEE)
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