Modeling and Algorithms to Simplify Complex Multi-Clock/Edge Timing Constraints in High Performance Synchronous Digital Circuits

Complex timing constraints that refer to multiple clocks and/or edges are often used in the design of modern high-performance processors. Such constraints complicate downstream algorithms such as logic synthesis and lead to inefficiencies. The complexity of the overall CAD system can be reduced considerably if we can optimally transform the timing constraints so that they refer only to a single clock and edge. In this dissertation, we show how to model these multi clock/edge timing constraints and describe algorithms to reduce the number of reference clocks/edges. We first introduce the concept of timing specification transformation and define optimality. We formulate a new optimization problem, which is important but has never been addressed by CAD researchers. We identify conditions under which this transformation can be performed efficiently without any loss of timing budget. We address the important problems of accurately handling signal transitions, sequential elements, input slope variations and timing overrides. The algorithm can be used to simplify the constraints to drive many synthesis and optimization algorithms. Finally, we take a holistic look at the traditional cell-based design flow and identify a significant problem which can be addressed by re-synthesis of carefully selected regions. We describe algorithms to identify such regions of the circuit. When these regions have interface timing specs that refer to multiple clocks/edges, we can use our previous algorithms to reduce them so that they can be efficiently re-synthesized.