Hardware implementation of parallel algorithm for setting up Benes networks

Citation data:

22nd International Conference on Parallel and Distributed Processing Techniques and Applications, Vol: 2016, Page: 10-16

Publication Year:
2016
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Repository URL:
https://digitalscholarship.unlv.edu/ece_fac_articles/902
Author(s):
Jiang, Yikun; Yang, Mei
conference paper description
Benes/Clos networks have been used in many areas, such as interconnection network in parallel computers, multiprocessors system, and networks-on-chip. The parallel switch setting algorithm is the key to satisfy the requirements of high performance switching networks. The Lee’s routing algorithm is by far the most efficient parallel routing algorithm for Benes networks. However, there is no hardware implementation for this algorithm. In this paper, the Lee’s routing algorithm is fully implemented in RTL and synthesized. We have refined the algorithm in data structure and initialization/updating of relation values to make it suitable for hardware implementation. The simulation and synthesis results of the switching setting circuits for 8x8 to 32x32 Benes networks confirm that the timing, area, and power consumption of the circuit is consistent with the complexity of the Lee’s algorithm. To the best of our knowledge, this is the first complete hardware implementation of the parallel switch setting algorithm which can handle all types of permutations including partial ones.