FPGA-based acceleration of the RMAP short read mapping tool

Publication Year:
2013
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Downloads 471
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Repository URL:
https://lib.dr.iastate.edu/etd/12991
DOI:
10.31274/etd-180810-3531
Author(s):
Mhapsekar, Pooja N.
Publisher(s):
Iowa State University
Tags:
Convey; FPGA; HC-1; RMAP; short read mapping
thesis / dissertation description
Bioinformatics is a quickly emerging field. Next generation sequencing technologies are producing data up to several gigabytes per day, making bioinformatics applications increasingly computationally intensive. In order to achieve greater speeds for processing this data, various techniques have been developed. These techniques involve parallelizing algorithms and/or spreading data across many computing nodes composed of devices such as Microprocessors, Graphics Processing Units (GPUs), and Field Programmable Gate Arrays (FPGAs).In this thesis, an FPGA is used to accelerate a bioinformatics application called RMAP, which is used for Short-Read Mapping. The most computationally intensive function in RMAP, the read mapping function, is implemented on the FPGA's reconfigurable hardware fabric. This is a first step in a larger effort to develop a more optimal hardware/software co-design for RMAP.The Convey HC-1 Hybrid Computing System was used as the platform for development. The short-read mapping functionality of RMAP was implemented on one of the four Xilinx Virtex 5 FPGAs available in the HC-1 system. The RMAP 2.0 software was rewritten to separate the read mapping function to facilitate its porting over to hardware. The implemented design was evaluated by varying input parameters such as genome size and number of reads. In addition, the hardware design was analyzed to find potential bottlenecks. The implementation results showed a speedup of ~5x using datasets with varying number of reads and a fixed reference genome, and ~2x using datasets with varying genome size and a fixed number of reads, for the hardware-implemented short-read mapping function of RMAP.