Active common-mode voltage reduction in a fault-tolerant three-phase inverter

Citation data:

Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC, Vol: 2016-May, Page: 2821-2825

Publication Year:
2016
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Abstract Views 7
Captures 3
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Repository URL:
https://scholarworks.boisestate.edu/electrical_facpubs/331
DOI:
10.1109/apec.2016.7468264
Author(s):
Mohammadi, Danyal; Ahmed-Zaid, Said
Publisher(s):
Institute of Electrical and Electronics Engineers (IEEE)
Tags:
Engineering; circuit faults; topology; inverters; fault tolerance; fault tolerant systems; switches; thyristors; Electrical and Computer Engineering
conference paper description
A fault-tolerant topology in a three-phase four-leg inverter which is capable of reducing the common-mode voltage (CMV) during the post-fault condition is presented. The CMV during both post-fault and pre-fault is investigated. This paper proposes a topology to reduce the common-mode voltage during pre- and post-fault operation of the inverter by using the healthy switches. The accompanying simulation results verify the common-mode current reduction during the fault period.