Accelerating Neural Networks Using Open Standard Software on RISC-V

Deep neural networks have the ability to learn patterns from huge amounts of data and hence have been adopted in many high performance computing and scientific applications. To achieve cost effective performance on such applications, vendors and chip designers are increasingly looking at domain-specific accelerators. To facilitate adapting the design to the needs of the workload, we need a generic open standard solution all through the stack - software to hardware. This paper explores one such approach. On the hardware side, RISC-V ISA has a minimal base integer set and provides custom extensions which works as a good starting point for designing these special accelerators. This design can further benefit from the RISC-V vector extensions which help achieving high compute density leading to performance improvement for user applications. On the software side, SYCL provides a C++-based portable parallel programming model to target various devices. Thus, enabling SYCL applications to run on RISC-V accelerators provides an open standard way of accelerating neural networks. This paper elaborates the usage of open standards and open source technology to run complex SYCL applications on RISC-V vector processors.