Analog CMOS circuits implementing neural segmentation model based on symmetric STDP learning
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), ISSN: 0302-9743, Vol: 4985 LNCS, Issue: PART 2, Page: 117-126
2008
- 6Citations
- 5Captures
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Conference Paper Description
We proposed a neural segmentation model that is suitable for implementation in analog VLSIs using conventional CMOS technology. The model consists of neural oscillators mutually couple through synaptic connections. The model performs segmentation in temporal domain, which is equivalent to segmentation according to the spike timing difference of each neuron. Thus, the learning is governed by symmetric spike-timing dependent plasticity (STDP). We numerically demonstrate basic operations of the proposed model as well as fundamental circuit operations using a simulation program with integrated circuit emphasis (SPICE). © 2008 Springer-Verlag Berlin Heidelberg.
Bibliographic Details
http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=54049146999&origin=inward; http://dx.doi.org/10.1007/978-3-540-69162-4_13; http://link.springer.com/10.1007/978-3-540-69162-4_13; http://link.springer.com/content/pdf/10.1007/978-3-540-69162-4_13.pdf; http://www.springerlink.com/index/10.1007/978-3-540-69162-4_13; http://www.springerlink.com/index/pdf/10.1007/978-3-540-69162-4_13; https://dx.doi.org/10.1007/978-3-540-69162-4_13; https://link.springer.com/chapter/10.1007/978-3-540-69162-4_13
Springer Science and Business Media LLC
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