Design and DC Electrical Performance Analysis of SOI-Based SiO/HfO Dual Dielectric Gate-All-Around Vertically Stacked Nanosheet at 5 nm Node
Lecture Notes in Electrical Engineering, ISSN: 1876-1119, Vol: 1024 LNEE, Page: 763-772
2023
- 1Citations
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Example: if you select the 1-year option for an article published in 2019 and a metric category shows 90%, that means that the article or review is performing better than 90% of the other articles/reviews published in that journal in 2019. If you select the 3-year option for the same article published in 2019 and the metric category shows 90%, that means that the article or review is performing better than 90% of the other articles/reviews published in that journal in 2019, 2018 and 2017.
Citation Benchmarking is provided by Scopus and SciVal and is different from the metrics context provided by PlumX Metrics.
Metrics Details
- Citations1
- Citation Indexes1
Conference Paper Description
In this paper, gate-all-around vertically stacked triple nanosheet transistor is explored for dc electrical performance for 5 nm node. Structure provides superior electrical properties, including high on-current of 61.7 µA, low leakage current of 20.6 × 10 A, high switching ratio (I/I = 2.99 × 10, steep sub-threshold slope (SS = 65.43 mV/decade) and very low drain induced barrier lowering (DIBL = 9.67 mV/V). The device gives excellent off state characteristics and shows promising results for sub-5 nm technology node. Nanosheet FET has been recognized as next generation device for improved power performance and area scaling compared to FinFET.
Bibliographic Details
http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=85168774632&origin=inward; http://dx.doi.org/10.1007/978-981-99-0973-5_58; https://link.springer.com/10.1007/978-981-99-0973-5_58; https://dx.doi.org/10.1007/978-981-99-0973-5_58; https://link.springer.com/chapter/10.1007/978-981-99-0973-5_58
Springer Science and Business Media LLC
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