Low capacitance and highly reliable blind through-silicon-vias (TSVs) with vacuum-assisted spin coating of polyimide dielectric liners

Low-k and high aspect ratio blind through-silicon-vias (TSVs) to be applied in “via-last/backside via” 3-D integration paradigm were fabricated with polyimide dielectric liners formed by vacuum-assisted spin coating technique. MIS trench capacitors with diameter of ~6 μm and depth of ~54 μm were successfully fabricated with polyimide insulator step coverage better than 30%. C-V characteristics and leakage current properties of the MIS trench capacitor were evaluated under thermal treatment. Experimental results show that, the minimum capacitance density is around 4.82 nF/cm, and the leakage current density after 30 cycles of thermal chock tests becomes stable and it is around 30 nA/cm under bias voltage of 20 V. It also shows that, the polyimide dielectric liner is with an excellent capability in constraining copper ion diffusion and mobile charges even under test temperature as high as 125°C. Finite element analysis results show that TSVs with polyimide dielectric liner are with lower risks in SiO interlayer dielectric (ILD) fracture and interfacial delamination along dielectric-silicon interface, thus, higher thermo-mechanical reliability can be expected.