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Fpga-based SoC design for real-time facial point detection using deep convolutional neural networks with dynamic partial reconfiguration

Signal, Image and Video Processing, ISSN: 1863-1711, Vol: 18, Issue: Suppl 1, Page: 599-615
2024
  • 0
    Citations
  • 0
    Usage
  • 2
    Captures
  • 1
    Mentions
  • 0
    Social Media
Metric Options:   Counts1 Year3 Year

Metrics Details

  • Captures
    2
  • Mentions
    1
    • News Mentions
      1
      • 1

Most Recent News

Reports on Networks Findings from University of Monastir Provide New Insights (Fpga-based Soc Design for Real-time Facial Point Detection Using Deep Convolutional Neural Networks With Dynamic Partial Reconfiguration)

2024 JUN 11 (NewsRx) -- By a News Reporter-Staff News Editor at Network Daily News -- Research findings on Networks are discussed in a new

Article Description

Deep convolutional neural networks (DCNNs) have been mainly powerful and important artificial intelligence techniques, which are exploited in various computer vision applications, such as facial point detection (FPD), owing their versatility and high performance. The role of DCNNs in this area is pivotal due to their ability to learn hierarchical features, which are essential for recognizing complex patterns. On the other hand, DCNNs have considerable computational complexity due to their topology nature. An FPGA-based SoC design is needed for CNN acceleration due to the rapid development, energy efficiency, low latency and high reconfigurability of FPGAs. Despite their performance benefits, FPGA-based SoCs also come with several limitations like complexity of design. This paper proposes a dynamic partial reconfiguration (DPR) and hybrid architecture for DCNN accelerators. We propose (i) a GPU-based software implementation for DCNN-based FPD, (ii) a CNN-based acceleration and optimization method using the high-level synthesis technique, (iii) a DPR-based hybrid architecture to improve the performance of the suggested approach. To validate our design, four scenarios are put forward. The experimental results prove that the proposed work achieves a better performance in terms of reconfigurability and execution time, hardware cost, and power consumption.

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