Linearity and Analog Performance Analysis of Silicon Junctionless Bulk FinFET Considering Gate Electrode Workfunction Variability and Different Fin Aspect Ratio

In case of conventional MOSFET structures, Short-Channel Effects (SCEs) are key issues for device performance as dimensions of these devices are reaching nanometer scales following scaling rules. SCEs affect the device characteristics and circuit performance designed with the nanoscale MOSFETs. MOSFETs with Fin-type channel (FinFET) are promising substitute for conventional devices at the nanoscale because of its better gate controlling power and immunity to SCEs. The gate electrode work function also becomes a vital role in the control of the threshold voltage (V). An analysis on the influence of Gate work function and Fin geometrical dimensions such as Fin aspect ratio which is defined as Fin height/Fin width, on the different electrical performance parameters of the Junctionless bulk FinFET is analyzed for its application in System-on-Chip (SoC). Few vital performance Figure of Merits (FoMs) have been explored by means of TCAD device simulator. With the aim of having a clear idea of the impact of device design parameters under study on device performance like ON current (I), I/I ratio, Transconductance (g), Transconductance Generation Factor (g/I), Cut-off Frequency (f) and Maximum frequency of oscillation (f) along with linearity performance parameters are studied. From simulated results, it is recognized that the device displays better I, I, I/I, Transconductance, and Transconductance generation factor when the device structure consists of higher Fin aspect ratio. However, minor reduction in f and f are observed with the structure having higher Fin aspect ratio. Effect of Gate material work function and Fin aspect ratio on device performance is established in this work. Outcomes of this work will be supportive to design FinFET with better performance for its specific applications.