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Parametric yield optimization of MOS IC's affected by device mismatch

Analog Integrated Circuits and Signal Processing, ISSN: 0925-1030, Vol: 29, Issue: 3, Page: 181-199
2001
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Article Description

In this paper a statistical design procedure for the parametric yield optimization based on Simulated Annealing and Quasi-Newton algorithms is presented. A rigorous formulation of the yield taking into account both inter-die and intra-die (mismatch) device variations has been used in defining the procedure steps. A reduction in the complexity of the yield optimization algorithm is achieved by performing a screening of the parameters, discarding those having small effect on the required performance. Application examples evidence the achievement of the method.

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