Parametric yield optimization of MOS IC's affected by device mismatch
Analog Integrated Circuits and Signal Processing, ISSN: 0925-1030, Vol: 29, Issue: 3, Page: 181-199
2001
- 2Citations
- 9Captures
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Example: if you select the 1-year option for an article published in 2019 and a metric category shows 90%, that means that the article or review is performing better than 90% of the other articles/reviews published in that journal in 2019. If you select the 3-year option for the same article published in 2019 and the metric category shows 90%, that means that the article or review is performing better than 90% of the other articles/reviews published in that journal in 2019, 2018 and 2017.
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Article Description
In this paper a statistical design procedure for the parametric yield optimization based on Simulated Annealing and Quasi-Newton algorithms is presented. A rigorous formulation of the yield taking into account both inter-die and intra-die (mismatch) device variations has been used in defining the procedure steps. A reduction in the complexity of the yield optimization algorithm is achieved by performing a screening of the parameters, discarding those having small effect on the required performance. Application examples evidence the achievement of the method.
Bibliographic Details
http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=0035546472&origin=inward; http://dx.doi.org/10.1023/a:1011213414261; http://link.springer.com/10.1023/A:1011213414261; http://dx.doi.org/10.1023/a%3A1011213414261; https://dx.doi.org/10.1023/a%3A1011213414261; https://link.springer.com/article/10.1023%2FA%3A1011213414261
Springer Nature
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