Improving effective yield through error tolerant system design
Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, Page: 1-4
2005
- 12Citations
- 6Captures
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Example: if you select the 1-year option for an article published in 2019 and a metric category shows 90%, that means that the article or review is performing better than 90% of the other articles/reviews published in that journal in 2019. If you select the 3-year option for the same article published in 2019 and the metric category shows 90%, that means that the article or review is performing better than 90% of the other articles/reviews published in that journal in 2019, 2018 and 2017.
Citation Benchmarking is provided by Scopus and SciVal and is different from the metrics context provided by PlumX Metrics.
Conference Paper Description
This paper illustrates that the effective chip yield (memory) can be improved up to 10x by incorporating error tolerance in the system design rather than incorporating design for yield at the circuit stage. The proposed approach leverages the fact that some applications - by construction - are inherently error tolerant and therefore do not require a strict bound of 100% correctness to function. This concept is elaborated upon using a wireless communication system framework as a case study for application aware yield enhancement.
Bibliographic Details
Institute of Electrical and Electronics Engineers (IEEE)
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