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Instruction merging to increase parallelism in VLIW architectures

2009 International Symposium on System-on-Chip - Proceedings, SoC 2009, Page: 143-146
2009
  • 7
    Citations
  • 0
    Usage
  • 0
    Captures
  • 0
    Mentions
  • 0
    Social Media
Metric Options:   Counts1 Year3 Year

Metrics Details

  • Citations
    7
    • Citation Indexes
      7

Conference Paper Description

This paper describes a new mechanism for concurrent use of more functional units, without increasing the control path of a generic VLIW architecture. The proposed approach only requires small modifications in the architecture and a new code selection function in the instruction scheduler. The key idea of this approach is to search for similar independent operations inside a basic assembler code block and merge them in a single instruction, which executes the same operation with even and odd operand registers in two different functional units. A comprehensive evaluation of this mechanism with two multimedia tasks shows an improvement of the dynamic instructions-per-cycle, exceeding the theoretical maximum of the reference architecture. ©2009 IEEE.

Bibliographic Details

Guillermo Payá-Vayá; Javier Martín-Langerwerf; Florian Giesemann; Holger Blume; Peter Pirsch

Institute of Electrical and Electronics Engineers (IEEE)

Computer Science; Engineering

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