Split-SAR ADCs: Improved linearity with power and speed optimization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN: 1063-8210, Vol: 22, Issue: 2, Page: 372-383
2014
  • 56
    Citations
  • 0
    Usage
  • 58
    Captures
  • 0
    Mentions
  • 0
    Social Media
Metric Options:   Counts1 Year3 Year

Metrics Details

  • Citations
    56
    • Citation Indexes
      56
  • Captures
    58

Article Description

This paper presents the linearity analysis of a successive approximation registers (SAR) analog-to-digital converters (ADC) with split DAC structure based on two switching methods: conventional charge-redistribution and V -based switching. The static linearity performance, namely the integral nonlinearity and differential nonlinearity, as well as the parasitic effects of the split DAC, are analyzed hereunder. In addition, a code-randomized calibration technique is proposed to correct the conversion nonlinearity in the conventional SAR ADC, which is verified by behavioral simulations, as well as measured results. Performances of both switching methods are demonstrated in 90 nm CMOS. Measurement results of power, speed, and linearity clearly show the benefits of using V-based switching. © 1993-2012 IEEE.

Bibliographic Details

Yan Zhu; Chi Hang Chan; U. Fat Chio; Sai Weng Sin; P. Seng-Pan; Rui Paulo Martins; Franco Maloberti

Institute of Electrical and Electronics Engineers (IEEE)

Computer Science; Engineering

Provide Feedback

Have ideas for a new metric? Would you like to see something else here?Let us know