Split-SAR ADCs: Improved linearity with power and speed optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN: 1063-8210, Vol: 22, Issue: 2, Page: 372-383
2014
- 56Citations
- 58Captures
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Article Description
This paper presents the linearity analysis of a successive approximation registers (SAR) analog-to-digital converters (ADC) with split DAC structure based on two switching methods: conventional charge-redistribution and V -based switching. The static linearity performance, namely the integral nonlinearity and differential nonlinearity, as well as the parasitic effects of the split DAC, are analyzed hereunder. In addition, a code-randomized calibration technique is proposed to correct the conversion nonlinearity in the conventional SAR ADC, which is verified by behavioral simulations, as well as measured results. Performances of both switching methods are demonstrated in 90 nm CMOS. Measurement results of power, speed, and linearity clearly show the benefits of using V-based switching. © 1993-2012 IEEE.
Bibliographic Details
Institute of Electrical and Electronics Engineers (IEEE)
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