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Relaxing state-access constraints in stateful programmable data planes

Computer Communication Review, ISSN: 1943-5819, Vol: 48, Issue: 1, Page: 3-9
2018
  • 6
    Citations
  • 0
    Usage
  • 15
    Captures
  • 0
    Mentions
  • 0
    Social Media
Metric Options:   Counts1 Year3 Year

Metrics Details

  • Citations
    6
    • Citation Indexes
      6
  • Captures
    15

Article Description

Supporting programmable stateful packet forwarding functions in hardware requires a tight balance between functionality and performance. Current state-of-the-art solutions are based on a very conservative model that assumes worst-case workloads. This finally limits the programmability of the system, even if actual deployment conditions may be very different from the worst-case scenario. We use trace-based simulations to highlight the benefits of accounting for specific workload characteristics. Furthermore, we show that relatively simple additions to a switching chip design can take advantage of such characteristics. In particular, we argue that introducing stalls in the switching chip pipeline enables stateful functions to be executed in a larger but bounded time without harming the overall forwarding performance. Our results show that, in some cases, the stateful processing of a packet could use 30x the time budget provided by state of the art solutions.

Bibliographic Details

Carmelo Cascone; Salvatore Pontarelli; Roberto Bifulco; Antonio Capone

Association for Computing Machinery (ACM)

Computer Science

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