Embedded Hardware Circuit and Software Development of USB based Hardware Accelerator
International Journal of Reconfigurable and Embedded Systems (IJRES), ISSN: 2089-4864, Vol: 7, Issue: 1
2018
- 7Captures
- 1Mentions
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Example: if you select the 1-year option for an article published in 2019 and a metric category shows 90%, that means that the article or review is performing better than 90% of the other articles/reviews published in that journal in 2019. If you select the 3-year option for the same article published in 2019 and the metric category shows 90%, that means that the article or review is performing better than 90% of the other articles/reviews published in that journal in 2019, 2018 and 2017.
Citation Benchmarking is provided by Scopus and SciVal and is different from the metrics context provided by PlumX Metrics.
Metrics Details
- Captures7
- Readers7
- Mentions1
- News Mentions1
- 1
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Embedded Hardware Circuit and Software Development of USB based Hardware Accelerator
1 view Share Like Download ... Published on Oct 16, 2020 This paper focus on design and develop a Hardware Accelerator which can plug in
Article Description
This paper focus on design and develop a Hardware Accelerator which can plug in to Universal Serial Bus of any modern low power low cost embedded development system to do complex processing in a plug and play development environment. Cryptographic algorithms, steganography and encoding decoding applications can use co-devices to accelerate performance. In this paper an implementation of a hardware infrastructure for computing though USB bus of any small scale embedded controller board. Execution engine of the accelerator will be an FPGA which is connected to a USB controller with DDR memory to store user data. FPGAs can perform the process faster than low power microcontrollers to solve such algorithms. For the implementation XILINX ARTIX 7 FPGA is used to off load the algorithm for faster processing. System also has a Cypress USB interface chip for offloading data path. Hardware also has a DRAM memory for dumping the data to be stored. Design also explores different futuristic features like interrupt connection for faster response path, shared memory architecture for hand shake mechanism and GPIO connection for implementation of faster interfaces for IO expansion.
Bibliographic Details
http://ijres.iaescore.com/index.php/IJRES/article/view/13489; http://ijres.iaescore.com/index.php/IJRES/article/viewFile/13489/pdf_1; http://dx.doi.org/10.11591/ijres.v7.i1.pp21-33; https://zenodo.org/record/3894115; https://dx.doi.org/10.11591/ijres.v7.i1.pp21-33; https://ijres.iaescore.com/index.php/IJRES/article/view/13489
Institute of Advanced Engineering and Science
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