Electrical characterization of interface defects in MOS structures containing silicon nanoclusters
Advanced Materials Research, ISSN: 1662-8985, Vol: 976, Page: 129-132
2014
- 1Citations
- 9Captures
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Conference Paper Description
The effect of annealing temperature on the properties of c-Si wafer/SiO interface (x = 1.15 and 1.3) is studied by Transmission Electron Microscopy and Capacitance/Conductance-Voltage measurements. Furnace annealing for 60 min at 700 and 1000°C is used to grow amorphous or crystalline Si nanoparticles. The high temperature process leads to an epitaxial overgrowth of the Si wafer and an increase of the interface roughness, 3-4 monolayers at 700°C and 4-5 monolayers at 1000 °C. The increased surface roughness is in correlation with the higher density of electrically active interface states. © (2014) Trans Tech Publications, Switzerland.
Bibliographic Details
http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=84904197120&origin=inward; http://dx.doi.org/10.4028/www.scientific.net/amr.976.129; http://www.scientific.net/AMR.976.129; http://www.scientific.net/AMR.976.129.pdf; https://www.scientific.net/AMR.976.129; https://dx.doi.org/10.4028/www.scientific.net/amr.976.129
Trans Tech Publications
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